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https://github.com/alliedmodders/sourcemod.git
synced 2025-12-06 18:08:36 +00:00
Add 64-bit opcodes.
This commit is contained in:
David Anderson
parent
8c9c1e3a6c
commit
653faba33a
@ -430,6 +430,16 @@ class AssemblerX86 : public Assembler
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void shrl(const Operand &dest, uint8_t imm) {
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shift_imm(dest, 5, imm);
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}
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void sall_cl(Register dest) {
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shift_cl(dest.code, 4);
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}
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void sall(Register dest, uint8_t imm) {
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shift_imm(dest.code, 4, imm);
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}
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void sall(const Operand &dest, uint8_t imm) {
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shift_imm(dest, 4, imm);
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}
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void sarl_cl(Register dest) {
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shift_cl(dest.code, 7);
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}
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@ -440,6 +450,19 @@ class AssemblerX86 : public Assembler
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shift_imm(dest, 7, imm);
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}
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void shldl_cl(Register op2, const Operand &op1) {
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emit2(0x0f, 0xa5, op2.code, op1);
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}
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void shldl_cl(Register op2, Register op1) {
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emit2(0x0f, 0xa5, op2.code, op1.code);
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}
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void shrdl_cl(Register op2, const Operand &op1) {
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emit2(0x0f, 0xad, op2.code, op1);
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}
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void shrdl_cl(Register op2, Register op1) {
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emit2(0x0f, 0xad, op2.code, op1.code);
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}
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void cmpl(Register left, int32_t imm) {
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alu_imm(7, imm, Operand(left));
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}
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@ -520,6 +543,25 @@ class AssemblerX86 : public Assembler
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alu_imm(0, imm, dest);
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}
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void adcl(const Operand &dest, Register src) {
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emit1(0x11, src.code, dest);
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}
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void adcl(Register dest, const Operand &src) {
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emit1(0x13, dest.code, src);
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}
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void adcl(Register dest, int32_t imm) {
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alu_imm(2, imm, Operand(dest));
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}
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void adcl(const Operand &dest, int32_t imm) {
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alu_imm(2, imm, dest);
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}
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void sbbl(const Operand &dest, Register src) {
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emit1(0x19, src.code, dest);
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}
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void sbbl(Register dest, const Operand &src) {
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emit1(0x1b, dest.code, src);
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}
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void imull(Register dest, const Operand &src) {
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emit2(0x0f, 0xaf, dest.code, src);
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}
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@ -551,6 +593,10 @@ class AssemblerX86 : public Assembler
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void testl(Register op1, Register op2) {
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emit1(0x85, op2.code, op1.code);
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}
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void testl(Register op1, int32_t imm) {
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emit1(0xf7, 0, op1.code);
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writeInt32(imm);
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}
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void set(ConditionCode cc, const Operand &dest) {
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emit2(0x0f, 0x90 + uint8_t(cc), 0, dest);
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}
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@ -245,17 +245,20 @@ namespace sp {
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_(RND_F32_TO_FLOOR, "floor.f32") \
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_(RND_F32_TO_CEIL, "ceil.f32") \
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_(RND_F32_TO_ZERO, "rndtozero.f32") \
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_(CMP_F32, "cmp.f32") \
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_(GT_F32, "gt.f32") \
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_(GE_F32, "ge.f32") \
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_(LT_F32, "lt.f32") \
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_(LE_F32, "le.f32") \
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_(NE_F32, "ne.f32") \
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_(EQ_F32, "eq.f32") \
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_(NOT_F32, "not.f32") \
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_(AND_C, "and.c") \
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_(ZEX_PRI, "zex.pri") \
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_(ZEX_ALT, "zex.alt")
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_(CMP_F32, "cmp.f32") \
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_(GT_F32, "gt.f32") \
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_(GE_F32, "ge.f32") \
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_(LT_F32, "lt.f32") \
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_(LE_F32, "le.f32") \
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_(NE_F32, "ne.f32") \
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_(EQ_F32, "eq.f32") \
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_(NOT_F32, "not.f32") \
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_(AND_C, "and.c") \
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_(ZEX_PRI, "zex.pri") \
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_(ZEX_ALT, "zex.alt") \
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_(PREFIX_I64, "prefix.i64") \
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_(SMODULO, "smod") \
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_(UMODULO, "umod")
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enum OPCODE {
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#define _(op, text) OP_##op,
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@ -1463,6 +1463,9 @@ Compiler::emitOp(OPCODE op)
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break;
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}
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case OP_PREFIX_I64:
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return emit64BitOp((OPCODE)readCell());
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case OP_NOP:
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break;
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@ -1474,6 +1477,270 @@ Compiler::emitOp(OPCODE op)
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return true;
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}
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static void
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div_i64_impl(int64_t *left, int64_t *right, int64_t *out)
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{
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*out = *left / *right;
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}
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#define DEFINE_CXX_I64_IMPL(name, type, op) \
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static void \
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name##_##type##_impl(type *left, type *right, type *out) \
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{ \
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*out = *left op *right; \
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}
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DEFINE_CXX_I64_IMPL(div, int64_t, /);
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DEFINE_CXX_I64_IMPL(div, uint64_t, /);
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DEFINE_CXX_I64_IMPL(mod, int64_t, %);
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DEFINE_CXX_I64_IMPL(mod, uint64_t, %);
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#define DEFINE_CXX_B64_IMPL(name, type, op) \
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static int \
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cmp_##type##_##name(type *left, type *right) \
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{ \
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return left op right; \
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}
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DEFINE_CXX_B64_IMPL(ge, int64_t, >=);
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DEFINE_CXX_B64_IMPL(gt, int64_t, >);
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DEFINE_CXX_B64_IMPL(lt, int64_t, <);
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DEFINE_CXX_B64_IMPL(le, int64_t, <=);
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DEFINE_CXX_B64_IMPL(ge, uint64_t, >=);
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DEFINE_CXX_B64_IMPL(gt, uint64_t, >);
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DEFINE_CXX_B64_IMPL(lt, uint64_t, <);
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DEFINE_CXX_B64_IMPL(le, uint64_t, <=);
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bool
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Compiler::emit64BitOp(OPCODE op)
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{
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// Binary ops:
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// stk+12 = left, high
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// stk+8 = left, low
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// stk+4 = right, high
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// stk+0 = right, low
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//
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// pri, alt may be used as scratch.
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switch (op) {
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case OP_ADD:
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ addl(Operand(stk, 8), eax);
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__ adcl(Operand(stk, 12), edx);
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__ addl(stk, 8);
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break;
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case OP_SUB:
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ subl(Operand(stk, 8), eax);
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__ sbbl(Operand(stk, 12), edx);
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__ addl(stk, 8);
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break;
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case OP_SMUL:
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case OP_UMUL:
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{
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// Perform the multiply in three steps, then add the results.
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const Register right_lo = edx;
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const Register right_hi = ebx;
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const Register left_lo = eax;
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const Register left_hi = ecx;
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__ push(ebx);
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__ movl(right_lo, Operand(stk, 0));
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__ movl(right_hi, Operand(stk, 4));
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__ movl(left_lo, Operand(stk, 8));
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__ movl(left_hi, Operand(stk, 12));
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__ imull(right_hi, left_lo); // eax*ebx -> ebx
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__ imull(left_hi, right_lo); // edx*ecx -> ecx
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__ mul(right_lo); // eax*edx -> eax:edx
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__ addl(ecx, ebx); // ecx += ebx
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__ addl(edx, ecx); // edx += ecx
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__ pop(ebx);
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__ addl(stk, 8);
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break;
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}
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case OP_SDIV:
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case OP_UDIV:
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case OP_UMODULO:
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case OP_SMODULO:
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__ cmpl(Operand(stk, 0), 0);
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__ j(zero, &error_divide_by_zero_);
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__ cmpl(Operand(stk, 4), 0);
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__ j(zero, &error_divide_by_zero_);
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__ lea(eax, Operand(stk, 0));
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__ lea(edx, Operand(stk, 8));
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__ push(edx);
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__ push(eax);
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__ push(edx);
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if (op == OP_SDIV)
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__ call(ExternalAddress((void *)div_int64_t_impl));
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else if (op == OP_UDIV)
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__ call(ExternalAddress((void *)div_uint64_t_impl));
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else if (op == OP_SMODULO)
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__ call(ExternalAddress((void *)mod_int64_t_impl));
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else if (op == OP_UMODULO)
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__ call(ExternalAddress((void *)mod_uint64_t_impl));
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__ addl(esp, 12);
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__ addl(stk, 8);
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break;
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case OP_AND:
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ andl(Operand(stk, 8), eax);
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__ andl(Operand(stk, 12), edx);
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__ addl(stk, 8);
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break;
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case OP_OR:
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ orl(Operand(stk, 8), eax);
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__ orl(Operand(stk, 12), edx);
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__ addl(stk, 8);
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break;
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case OP_XOR:
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ xorl(Operand(stk, 8), eax);
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__ xorl(Operand(stk, 12), edx);
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__ addl(stk, 8);
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break;
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case OP_SGRTR:
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case OP_SLESS:
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case OP_LESS:
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case OP_GRTR:
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case OP_LEQ:
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case OP_SLEQ:
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case OP_GEQ:
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case OP_SGEQ:
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__ lea(eax, Operand(stk, 0));
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__ lea(edx, Operand(stk, 8));
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__ push(edx);
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__ push(eax);
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switch (op) {
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case OP_SGRTR:
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__ call(ExternalAddress((void *)cmp_int64_t_gt));
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break;
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case OP_GRTR:
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__ call(ExternalAddress((void *)cmp_uint64_t_gt));
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break;
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case OP_SLESS:
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__ call(ExternalAddress((void *)cmp_int64_t_lt));
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break;
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case OP_LESS:
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__ call(ExternalAddress((void *)cmp_uint64_t_lt));
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break;
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case OP_SLEQ:
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__ call(ExternalAddress((void *)cmp_int64_t_le));
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break;
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case OP_LEQ:
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__ call(ExternalAddress((void *)cmp_uint64_t_le));
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break;
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case OP_SGEQ:
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__ call(ExternalAddress((void *)cmp_int64_t_ge));
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break;
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case OP_GEQ:
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__ call(ExternalAddress((void *)cmp_uint64_t_ge));
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break;
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}
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__ addl(esp, 8);
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__ addl(stk, 16);
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break;
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case OP_EQ:
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case OP_NEQ:
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{
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Label f, t;
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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__ cmpl(Operand(stk, 8), eax);
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__ j((op == OP_EQ) ? not_equal : equal, &f);
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__ cmpl(Operand(stk, 12), edx);
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__ j((op == OP_EQ) ? not_equal : equal, &f);
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__ movl(pri, 1);
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__ jmp(&t);
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__ bind(&f);
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__ xorl(pri, pri);
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__ bind(&t);
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break;
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}
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// shift is in pri
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case OP_SHL:
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{
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__ movl(ecx, pri);
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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Label done;
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__ shldl_cl(edx, eax); // :TODO: right order?
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__ sall_cl(eax);
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__ testl(eax, 0x20);
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__ j(zero, &done);
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__ movl(edx, eax);
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__ xorl(eax, eax);
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__ movl(eax, edx);
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__ xorl(edx, edx);
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__ bind(&done);
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__ movl(Operand(stk, 0), eax);
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__ movl(Operand(stk, 4), edx);
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break;
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}
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case OP_SHR:
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case OP_SSHR:
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{
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__ movl(ecx, pri);
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__ movl(eax, Operand(stk, 0));
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__ movl(edx, Operand(stk, 4));
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Label done;
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__ shrdl_cl(eax, edx); // :TODO: right order?
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if (op == OP_SHR)
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__ shrl_cl(edx);
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else if (op == OP_SSHR)
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__ sarl_cl(edx);
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__ testl(eax, 0x20);
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__ j(zero, &done);
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__ movl(eax, edx);
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__ xorl(edx, edx);
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__ bind(&done);
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__ movl(Operand(stk, 0), eax);
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__ movl(Operand(stk, 4), edx);
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break;
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}
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case OP_NEG:
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__ negl(Operand(stk, 0));
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__ adcl(Operand(stk, 4), 0);
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__ negl(Operand(stk, 4));
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break;
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case OP_INVERT:
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__ notl(Operand(stk, 0));
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__ notl(Operand(stk, 4));
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break;
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// i64 -> bool
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case OP_NOT:
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__ movl(eax, Operand(stk, 0));
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__ orl(eax, Operand(stk, 4));
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__ testl(eax, eax);
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__ movl(eax, 0);
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__ set(zero, r8_al);
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__ addl(stk, 8);
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break;
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default:
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error_ = SP_ERROR_INVALID_INSTRUCTION;
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return false;
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}
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return true;
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}
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Label *
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Compiler::labelAt(size_t offset)
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{
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@ -106,6 +106,7 @@ class Compiler
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void emitErrorPath(Label *dest, int code);
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void emitErrorPaths();
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void emitFloatCmp(ConditionCode cc);
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bool emit64BitOp(OPCODE op);
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ExternalAddress cipAddr() {
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sp_context_t *ctx = rt_->GetBaseContext()->GetCtx();
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