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Add sign and zero extension opcodes.

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This commit is contained in:
David Anderson 2014-12-14 22:49:34 -08:00
parent 4684cd5bac
commit 9006e61d65
2 changed files with 30 additions and 1 deletions
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4
sourcepawn/include/smx/smx-v1-opcodes.h
View File

@ -253,7 +253,9 @@ namespace sp {
_(NE_F32, "ne.f32") \
_(EQ_F32, "eq.f32") \
_(NOT_F32, "not.f32") \
_(AND_C, "and.c")
_(AND_C, "and.c") \
_(ZEX_PRI, "zex.pri") \
_(ZEX_ALT, "zex.alt")
enum OPCODE {
#define _(op, text) OP_##op,

27
sourcepawn/jit/x86/jit_x86.cpp
View File

@ -1015,6 +1015,33 @@ Compiler::emitOp(OPCODE op)
break;
}
// Zero-extend an [8,16] bit value to a 32-bit value, or a 32-bit value
// to a 64-bit value.
case OP_ZEX_PRI:
case OP_ZEX_ALT:
{
Register reg = (op == OP_SIGN_PRI) ? pri : alt;
size_t bits = readCell();
switch (bits) {
case 8:
__ movzxb(reg, reg);
break;
case 16:
__ movzxw(reg, reg);
break;
case 32:
// Address is in |reg|.
__ lea(tmp, Operand(reg, 4));
emitCheckAddress(tmp);
__ movl(Operand(reg, 4), 0);
break;
default:
error_= SP_ERROR_INVALID_INSTRUCTION;
return false;
}
break;
}
case OP_ABS_F32:
__ movl(pri, Operand(stk, 0));
__ andl(pri, 0x7fffffff);