From 9006e61d65286fd4da76613ecff5d8d3bc614527 Mon Sep 17 00:00:00 2001
From: David Anderson <dvander@alliedmods.net>
Date: Sun, 14 Dec 2014 22:49:34 -0800
Subject: [PATCH] Add sign and zero extension opcodes.

---
 sourcepawn/include/smx/smx-v1-opcodes.h |  4 +++-
 sourcepawn/jit/x86/jit_x86.cpp          | 27 +++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/sourcepawn/include/smx/smx-v1-opcodes.h b/sourcepawn/include/smx/smx-v1-opcodes.h
index b4eaa26e1..be91c5fda 100644
--- a/sourcepawn/include/smx/smx-v1-opcodes.h
+++ b/sourcepawn/include/smx/smx-v1-opcodes.h
@@ -253,7 +253,9 @@ namespace sp {
   _(NE_F32,        "ne.f32")       \
   _(EQ_F32,        "eq.f32")       \
   _(NOT_F32,       "not.f32")      \
-  _(AND_C,         "and.c")
+  _(AND_C,         "and.c")        \
+  _(ZEX_PRI,       "zex.pri")      \
+  _(ZEX_ALT,       "zex.alt")
 
 enum OPCODE {
 #define _(op, text) OP_##op,
diff --git a/sourcepawn/jit/x86/jit_x86.cpp b/sourcepawn/jit/x86/jit_x86.cpp
index 60f859c7b..b97dbd1b5 100644
--- a/sourcepawn/jit/x86/jit_x86.cpp
+++ b/sourcepawn/jit/x86/jit_x86.cpp
@@ -1015,6 +1015,33 @@ Compiler::emitOp(OPCODE op)
       break;
     }
 
+    // Zero-extend an [8,16] bit value to a 32-bit value, or a 32-bit value
+    // to a 64-bit value.
+    case OP_ZEX_PRI:
+    case OP_ZEX_ALT:
+    {
+      Register reg = (op == OP_SIGN_PRI) ? pri : alt;
+      size_t bits = readCell();
+      switch (bits) {
+        case 8:
+          __ movzxb(reg, reg);
+          break;
+        case 16:
+          __ movzxw(reg, reg);
+          break;
+        case 32:
+          // Address is in |reg|.
+          __ lea(tmp, Operand(reg, 4));
+          emitCheckAddress(tmp);
+          __ movl(Operand(reg, 4), 0);
+          break;
+        default:
+          error_= SP_ERROR_INVALID_INSTRUCTION;
+          return false;
+      }
+      break;
+    }
+
     case OP_ABS_F32:
       __ movl(pri, Operand(stk, 0));
       __ andl(pri, 0x7fffffff);